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e advance information june 1997 order number: 290609-001 n two 32-byte write buffers ? 2 m s per byte effective programming time n operating voltage ? 5v v cc ? 5v v pp n 70 ns read access time (16 mbit) 90 ns read access time (32 mbit) n high-density symmetrically-blocked architecture ? 32 64-kbyte erase blocks (16 mbit) ? 64 64-kbyte erase blocks (32 mbit) n system performance enhancements ? sts status output n industry-standard packaging ? ssop and tsop (16 mbit) ? ssop (32 mbit) n cross-compatible command support ? intel standard command set ? common flash interface (cfi) ? scaleable command set (scs) n 100,000 block erase cycles n enhanced data protection features ? absolute protection with v pp = gnd ? flexible block locking ? block erase/program lockout during power transitions n configurable x8 or x16 i/o n automation suspend options ? program suspend to read ? block erase suspend to program ? block erase suspend to read n etox? v nonvolatile flash technology intels word-wide flashfile? memory family provides high-density, low-cost, nonvolatile, read/write storage solutions for a wide range of applications. the word-wide memories are available at various densities in the same package type. their symmetrically-blocked architecture, voltage, and extended cycling provide highly flexible components suitable for resident flash arrays, simms, and memory cards. enhanced suspend capabilities provide an ideal solution for code or data storage applications. for secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to dram, the word-wide memories offer three levels of protection: absolute protection with v pp at gnd, selective block locking, and program/erase lockout during power transitions. these alternatives give designers ultimate control of their code security needs. this family of products is manufactured on intels 0.4 m m etox? v process technology. it comes in the industry-standard 56-lead ssop. in addition, the 16-mb device is available in the industry-standard 56-lead tsop package. word-wide flashfile? memory family 28f160s5, 28f320s5 includes extended temperature specifications
information in this document is provided in connection with intel products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantabili ty, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. the 28f160s5 and 28f320s5 may contain design defects or errors known as errata. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature, may be obtained from: intel corporation p.o. box 7641 mt. prospect, il 60056-7641 or call 1-800-879-4683 or visit intels website at http:\\www.intel.com copyright ? intel corporation, 1997 cg-041493 *third-party brands and names are the property of their respective owners.
e 28f160s5, 28f320s5 3 advance information contents page page 1.0 introduction .............................................5 1.1 new features...............................................5 1.2 product overview.........................................5 1.3 pinout and pin description ...........................6 2.0 principles of operation .......................9 2.1 data protection ..........................................10 3.0 bus operation .........................................11 3.1 read ..........................................................11 3.2 output disable ...........................................11 3.3 standby......................................................11 3.4 deep power-down .....................................11 3.5 read query operation ...............................11 3.6 read identifier codes operation ................12 3.7 write ..........................................................12 4.0 command definitions ............................12 4.1 read array command................................16 4.2 read query mode command.....................16 4.2.1 query structure output .......................16 4.2.2 query structure overview ...................18 4.2.3 block status register ..........................19 4.2.4 cfi query identification string.............20 4.2.5 system interface information..............21 4.2.6 device geometry definition .................22 4.2.7 intel-specific extended query table ...23 4.3 read identifier codes command ...............24 4.4 read status register command................24 4.5 clear status register command................25 4.6 block erase command ..............................25 4.7 full chip erase command .........................25 4.8 write to buffer command ...........................26 4.9 byte/word write command ........................26 4.10 sts configuration command...................27 4.11 block erase suspend command ..............27 4.12 program suspend command ...................27 4.13 set block lock-bit commands .................28 4.14 clear block lock-bits command ..............28 5.0 design considerations ........................38 5.1 three-line output control..........................38 5.2. sts and wsm polling ...............................38 5.3 power supply decoupling ..........................38 5.4 v pp trace on printed circuit boards...........38 5.5 v cc , v pp , rp# transitions..........................38 5.6 power-up/down protection ........................38 6.0 electrical specifications..................39 6.1 absolute maximum ratings........................39 6.2 operating conditions..................................39 6.2.1 capacitance.........................................40 6.2.2 ac input/output test conditions .........40 6.2.3 dc characteristics...............................41 6.2.4 ac characteristics - read-only operations..........................................43 6.2.5 ac characteristics - write operations .45 6.2.6 reset operations.................................47 6.2.7 erase, program, and lock-bit configuration performance.................48 appendix a: device nomenclature and ordering information ..................................49 appendix b: additional information ...............50
28f160s5, 28f320s5 e 4 advance information revision history number description -001 original version
e 28f160s5, 28f320s5 5 advance information 1.0 introduction this datasheet contains word-wide flashfile? memory (28f160s5, 28f320s5) specifications. section 1 provides a flash memory overview. sections 2, 3, 4, and 5 describe the memory organization and functionality. section 6 covers electrical specifications for extended temperature product offerings. 1.1 new features the word-wide flashfile memory family maintains basic compatibility with intels 28f016sa and 28f016sv. key enhancements include: common flash interface (cfi) support scaleable command set (scs) support s5 technology enhanced suspend capabilities they share a compatible status register, basic software commands, and pinout. these similarities enable a clean migration from the 28f016sa or 28f016sv. when upgrading, it is important to note the following differences: because of new feature and density options, the devices have different device identifier codes. this allows for software optimization. new software commands. to take advantage of the 5v technology on the 28f160s5 and 28f320s5, allow v pp connection to v cc . the 28f160s5 and 28f320s5 flashfile memories do not support a 12v v pp option. 1.2 product overview the word-wide flashfile memory family provides density upgrades with pinout compatibility for the 16- and 32-mbit densities. they are high- performance memories arranged as 1 mword and 2 mwords of 16 bits or 2 mbyte and 4 mbyte of 8 bits. this data is grouped in thirty-two and sixty- four 64-kbyte blocks that can be erased, locked, and unlocked in- system. figure 1 shows the block diagram, and figure 4 illustrates the memory organization. specifically designed for 5v systems, the 28f160s5 and 28f320s5 support read and write operation with v cc equal to v pp . coupled with this capability, high programming performance is achieved through small, highly-optimized write buffer operations. additionally, the dedicated v pp pin gives complete data protection when v pp v pplk . a common flash interface (cfi) permits oem- specified software algorithms to be used for entire families of devices. this allows device-independent, jedec id-independent, and forward- and backward-compatible software support for the specified flash device families. flash vendors can standardize their existing interfaces for long-term compatibility. scaleable command set (scs) allows a single, simple software driver in all host systems to work with all scs-compliant flash memory devices, independent of system-level packaging (e.g., memory card, simm, or direct-to-board placement). additionally, scs provides the highest system/device data transfer rates and minimizes device and system-level implementation costs. a command user interface (cui) serves as the interface between the system processor and internal device operation. a valid command sequence written to the cui initiates device automation. an internal write state machine (wsm) automatically executes the algorithms and timings necessary for block erase, program, and lock-bit configuration operations. a block erase operation erases one of the devices 64-kbyte blocks typically within t whqv2/ehqv2 independent of other blo cks. each block can be independently erased 100,000 times. block erase suspend allows system software to sus pend block erase to read or write data from any other block. data is programmed in byte, word or page increments. program suspend mode enables the system to r ead data or execute code from any other flash memory array location. the device incorporates two write buffers of 32 bytes (16 words) to allow optimum-performance data programming. this feature can improve system program performance by up to eight times over non-buffer programming.
28f160s5, 28f320s5 e 6 advance information individual block locking uses a combination of block lock-bits to lock and unlock blo cks. block lock-bits gate block erase, full chip erase, program and write to buffer operations. lock-bit configuration operations (set block lock-bit and clear block lock-bits commands) set and clear lock-bits. the status register and the sts pin in ry/by# mode indicate whether or not the device is busy executing an operation or ready for a new command. polling the status register, system software retrieves wsm feedback. sts in ry/by# mode gives an additional indicator of wsm activity by providing a hardware status signal. like the status register, ry/by#-low indicates that the wsm is performing a block erase, program, or lock- bit operation. ry/by#-high indicates that the wsm is ready for a new command, block erase is suspended (and program is inactive), program is suspended, or the device is in deep power-down mode. the automatic power savings (aps) feature substantially reduces active current when the device is in static mode (addresses not switching). the byte# pin allows either x8 or x16 read/writes to the device. byte# at logic low selects 8-bit mode with address a 0 selecting between the low byte and high byte. byte# at logic high enables 16-bit operation with address a 1 becoming the lowest order address. address a 0 is not used in 16- bit mode. when one of the ce x # pins (ce 0 #, ce 1 #) and rp# pins are at v cc , the component enters a cmos standby mode. driving rp# to gnd enables a deep power-down mode which significantly reduces power consumption, provides write protection, resets the device, and clears the status register. a reset time (t phqv ) is required from rp# switching high until outputs are valid. likewise, the device has a wake time (t phel ) from rp#-high until writes to the cui are recognized. 1.3 pinout and pin description the 16-mbit device is available in the 56-lead tsop and 56-lead ssop. the 32- mb device is available in the 56-lead ssop. the pinouts are shown in figures 2 and 3. 16-mbit: thirty-two 32-mbit: sixty-four 64-kbyte blocks input buffer output multiplexer y-gating program/erase voltage switch data comparator status register identifier register data register i/o logic address latch address counter x-decoder y-decoder input buffer output buffer gnd v cc v pp ce# we# oe# rp# wp# byte# command user interface 16-mbit: a 0 - a 20 32-mbit: a 0 - a 21 dq 0 - dq 15 v cc write buffer write state machine multiplexer query sts 0608_01 figure 1. 28f320s5 and 28f160s5 block diagram
e 28f160s5, 28f320s5 7 advance information table 1. pin descriptions sym type name and function a 0 Ca 21 input address inputs: address inputs for read and write operations are internally latched during a write cycle. a 0 selects high or low byte when operating in x8 mode. in x16 mode, a 0 is not used; input buffer is off. 16-mbit ? a 0 Ca 20 32-mbit ? a 0 Ca 21 dq 0 ? dq 15 input/ output data input/outputs: inputs data and commands during cui write cycles; outputs data during memory array, status register, query and identifier code read cycles. data pins float to high-impedance when the chip is deselected or outputs are disabled. data is internally latched during a write cycle. ce 0 #, ce 1 # input chip enable: activates the devices control logic, input buffers, decoders, and sense amplifiers. with ce 0 # or ce 1 # high, the device is deselected and power consumption reduces to standby levels. both ce 0 # and ce 1 # must be low to select the device. device selection occurs with the latter falling edge of ce 0 # or ce 1 #. the first rising edge of ce 0 # or ce 1 # disables the device. rp# input reset/deep power-down: when driven low, rp# inhibits write operations which provides data protection during system power transitions, puts the device in deep power-down mode, and resets internal automation. rp#-high enables normal operation. exit from deep power-down sets the device to read array mode. oe# input output enable: gates the devices outputs during a read cycle. we# input write enable: controls writes to the cui and array blocks. addresses and data are latched on the rising edge of the we# pulse. sts open drain output status: indicates the status of the internal state machine. when configured in level mode (default), it acts as a ry/by# pin. for this and alternate configurations of the status pin, see the configuration command. tie sts to v cc with a pull-up resistor. wp# input write protect: master control for block locking. when v il , locked blocks cannot be erased or programmed, and block lock-bits cannot be set or cleared. byte# input byte enable: configures x8 mode (low) or x16 mode (high). v pp supply block erase, program, lock-bit configuration power supply: necessary voltage to perform block erase, program, and lock-bit configuration operations. do not float any power pins. v cc supply device power supply: do not float any power pins. gnd supply ground: do not float any ground pins. nc no connect: lead is not internally connected; it may be driven or floated.
28f160s5, 28f320s5 e 8 advance information 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 56-lead tsop standard pinout 14 mm x 20 mm top view highlights pinout changes. wp# we# oe# ry/by# dq 15 dq 7 dq 14 dq 6 gnd dq 13 dq 5 dq 12 dq 4 v cc gnd dq 11 dq 3 dq 10 dq 2 v cc dq 9 dq 1 dq 8 dq 0 a 0 byte# nc nc 28f016sa 28f016sv ry/by# 3/5# ce 1 # nc a 20 a 19 a 18 a 17 a 16 v cc a 15 a 14 a 13 a 12 ce 0 # v pp rp# a 11 a 10 a 9 a 8 gnd a 7 a 6 a 5 a 4 a 3 a 2 a 1 28f016sa 28f016sv 3/5# nc ce 1 # nc a 20 a 19 a 18 a 17 a 16 v cc a 15 a 14 a 13 a 12 ce 0 # v pp rp# a 11 a 10 a 9 a 8 gnd a 7 a 6 a 5 a 4 a 3 a 2 a 1 28f160s3 28f160s5 wp# we# oe# sts dq 15 dq 7 dq 14 dq 6 gnd dq 13 dq 5 dq 12 dq 4 v cc gnd dq 11 dq 3 dq 10 dq 2 v cc dq 9 dq 1 dq 8 dq 0 a 0 byte# nc nc 28f160s3 28f160s5 0608_02 figure 2. 28f160s5 tsop 56-lead pinout
e 28f160s5, 28f320s5 9 advance information figure 3. 28f320s5 and 28f160s5 ssop 56-lead pinout 2.0 principles of operation the word-wide flashfile memories include an on-chip write state machine (wsm) to manage block erase, program, and lock-bit configuration functions. it allows for: 100% ttl-level control inputs, fixed power supplies during block erasure, programming, lock-bit configuration, and minimal processor overhead with ram-like interface timings. after initial device power-up or return from deep power-down mode (see bus operations), the device defaults to read array mode. manipulation of external memory control pins allow array read, standby, and output disable operations.
28f160s5, 28f320s5 e 10 advance information read array, status register, query, and identifier codes can be accessed through the cui independent of the v pp voltage. proper programming voltage on v pp enables successful block erasure, program, and lock-bit configuration. all functions associated with altering memory contents block erase, program, lock-bit configuration, status, and identifier codesare accessed via the cui and verified through the status register. commands are written using standard micro- processor write timings. the cui contents serve as input to the wsm that controls the block erase, programming, and lock-bit configuration. the internal algorithms are regulated by the wsm, including pulse repetition, internal verification, and margining of data. addresses and data are internally latched during write cycles. writing the appropriate command outputs array data, identifier codes, or status register data. interface software that initiates and polls progress of block erase, programming, and lock- bit configuration can be stored in any block. this code is copied to and executed from system ram during flash memory updates. after successful completion, reads are again possible via the read array command. block erase suspend allows system software to sus pend a block erase to read or write data from any other block. program suspend allows system software to suspend a program to read data from any other flash memory array location. 2.1 data protection depending on the application, the system designer may choose to make the v pp power supply switchable or hardwired to v pph . the device supports either design practice, and encourages optimization of the processor- memory interface. when v pp v pplk , memory contents cannot be altered. when high voltage is applied to v pp , the two-step block erase, program, or lock-bit configuration command sequences provide protection from unwanted operations. all write functions are disabled when v cc voltage is below the write lockout voltage v lko or when rp# is at v il . the devices block locking capability provides additional protection from inadvertent code or data alteration. 0608_05 figure 4. memory map
e 28f160s5, 28f320s5 11 advance information 3.0 bus operation the local cpu reads and writes flash memory in- system. all bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 3.1 read block information, query information, identifier codes and status registers can be read independent of the v pp voltage. the first task is to place the device into the desired read mode by writing the appropriate read-mode command (read array, query, read identifier codes, or read status register) to the cui. upon initial device power-up or after exit from deep power-down mode, the device automatically resets to read array mode. control pins dictate the data flow in and out of the component. ce 0 #, ce 1 # and oe# must be driven active to obtain data at the outputs. ce 0 # and ce 1 # are the device selection controls, and, when both are active, enable the selected memory device. oe# is the data output (dq 0 C dq 15 ) control: when active it drives the selected memory data onto the i/o bus. we# must be at v ih and rp# must be at v ih . figure 16 illustrates a read cycle. 3.2 output disable with oe# at a logic-high level (v ih ), the device outputs are disabled. output pins dq 0 Cdq 15 are placed in a high-impedance state. 3.3 standby ce 0 # or ce 1 # at a logic-high level (v ih ) places the device in standby mode, substantially reducing device power consumption. dq 0 Cdq 15 (or dq 0 C dq 7 in x8 mode) outputs are placed in a high-impedance state independent of oe#. if deselected during block erase, programming, or lock-bit configuration, the device continues functioning and consuming active power until the operation completes. 3.4 deep power-down rp# at v il initiates the deep power-down mode. in read mode, rp#-low deselects the memory, places output drivers in a high-impedance state, and turns off all internal circuits. rp# must be held low for time t plph . time t phqv is required after return from power-down until initial memory access outputs are valid. after this wake-up interval, normal operation is restored. the cui resets to read array mode, and the status register is set to 80h. during block erase, programming, or lock-bit configuration modes, rp#-low will abort the operation. sts in ry/by# mode remains low until the reset operation is complete. memory contents being altered are no longer valid; the data may be partially corrupted after programming or partially altered after an erase or lock-bit configuration. time t phwl is required after rp# goes to logic-high (v ih ) before another command can be written. it is important in any automated system to assert rp# during system reset. when the system comes out of reset, it expects to read from the flash memory. automated flash memories provide status information when accessed during block erase, programming, or lock-bit configuration modes. if a cpu reset occurs with no flash memory reset, proper cpu initialization may not occur because the flash memory may be providing status information instead of array data. intels flash memories allow proper cpu initialization following a system reset thr ough the use of the rp# input. in this application, rp# is controlled by the same reset# signal that resets the system cpu. 3.5 read query operation the read query operation outputs block status, common flash interface (cfi) id string, system interface, device geometry, and intel-specific extended query information.
28f160s5, 28f320s5 e 12 advance information 3.6 read identifier codes operation the read-identifier codes operation outputs the manufacturer code, device code, and block lock configuration codes for each block configuration (see figure 5). using the manufacturer and device codes, the system software can automatically match the device with its proper algorithms. the block-lock configuration codes identify each blocks lock-bit setting. 0608_06 figure 5. device identifier code memory map 3.7 write writing commands to the cui enables reading of device data, query, identifier codes, inspection and clearing of the status register. additionally, when v pp = v pph , block erasure, programming, and lock-bit configuration can also be performed. the block erase command requires appropriate command data and an address within the block to be erased. the byte/word write command requires the command and address of the location to be written. set block lock-bit commands require the command and address within the block to be locked. the clear block lock-bits command requires the command and an address within the device. the cui does not occupy an addressable memory location. it is written when we#, ce 0 #, and ce 1 # are active and oe# = v ih . the address and data needed to execute a command are latched on the rising edge of we# or ce x # (ce 0 #, ce 1 #), whichever goes high first. standard microprocessor write timings are used. figure 17 illustrates a write operation. 4.0 command definitions v pp voltage v pplk enables read operations from the status register, identifier codes, or memory blocks. placing v pph on v pp enables successful block erase, programming, and lock- bit configuration operations. device operations are selected by writing specific commands into the cui. table 2 and table 3 define these commands.
e 28f160s5, 28f320s5 13 advance information table 2. bus operations mode notes rp# ce 0 #ce 1 # oe# (11) we# (11) address v pp dq (8) sts (3) read 1,2 v ih v il v il v il v ih xxd out x output disable v ih v il v il v ih v ih x x high z x standby v ih v il v ih v ih v ih v il v ih x x x x high z x reset/power- down mode 10 v il x x x x x x high z high z (9) read identifier codes 4v ih v il v il v il v ih see figure 5 xd out high z (9) read query 5 v ih v il v il v il v ih see table 6 x d out high z (9) write 3,6,7 v ih v il v il v ih v il xv pph d in x notes: 1. refer to table 19. when v pp v pplk , memory contents can be read, but not altered. 2. x can be v il or v ih for control and address input pins and v pplk or v pph for v pp . see table 19, for v pplk and v pph voltages. 3. sts in ry/by# mode (default) is v ol when the wsm is executing internal block erase, programming, or lock-bit configuration algorithms. it is v oh when the wsm is not busy, in block erase suspend mode (with programming inactive), program suspend mode, or deep power-down mode. 4. see section 4.3 for read identifier code data. 5. see section 4.2 for read query data. 6. command writes involving block erase, write, or lock-bit configuration are reliably executed when v pp = v pph and v cc = v cc1/2 (see section 6.2). 7. refer to table 3 for valid d in during a write operation. 8. dq refers to dq 0 C7 if byte# is low and dq 0C15 if byte# is high. 9. high z will be v oh with an external pull-up resistor. 10. rp# at gnd 0.2v ensures the lowest deep power-down current. 11. oe# = v il and we# = v il concurrently is an undefined state and should not be attempted.
28f160s5, 28f320s5 e 14 advance information table 3 . word-wide flashfile? memory command set definitions (13) command scaleable or basic command set (14) bus c y cles req'd notes first bus cycle second bus cycle oper (1) addr (2) data (3,4) oper (1) addr (2) data (3,4) read array scs/bcs 1 write x ffh read identifier codes scs/bcs 3 2 5 write x 90h read ia id read query scs 3 2 write x 98h read qa qd read status register scs/bcs 2 write x 70h read x srd clear status register scs/bcs 1 write x 50h write to buffer scs > 2 8, 9, 10 write ba e8h write ba n word/byte program scs/bcs 2 6,7 write x 40h or 10h write pa pd block erase scs/bcs 2 6,10 write x 20h write ba d0h block erase, word/byte program suspend scs/bcs 1 6 write x b0h block erase, word/byte program resume scs/bcs 1 6 write x d0h sts pin configuration scs 2 write x b8h write x cc set block lock-bit scs 2 11 write x 60h write ba 01h clear block lock-bits scs 2 12 write x 60h write x d0h full chip erase scs 2 10 write x 30h write x d0h
e 28f160s5, 28f320s5 15 advance information notes: 1. bus operations are defined in.table 2. 2. x = any valid address within the device. ba = address within the block being erased or locked. ia = identifier code address: see table 12. qa = query database address. pa = address of memory location to be programmed. 3. id = data read from identifier codes. qd = data read from query database. srd = data read from status register. see table 15 for a description of the status register bits. pd = data to be programmed at location pa. data is latched on the rising edge of we#. cc = configuration code. (see table 14.) 4. the upper byte of the data bus (dq 8 C15 ) during command writes is a dont care in x16 operation. 5. following the read identifier codes command, read operations access manufacturer, device, and block-lock codes. see section 4.3 for read identifier code data. 6. if a block is locked (i.e., the blocks lock-bit is set to 0), wp# must be at v ih in order to perform block erase, program and suspend operations. attempts to issue a block erase, program and suspend operation to a locked block while wp# is v il will fail. 7. either 40h or 10h are recognized by the wsm as the byte/word program setup. 8. after the write to buffer command is issued, check the xsr to make sure a write buffer is available. 9. n = byte/word count argument such that the number of bytes/words to be written to the input buffer = n + 1. n = 0 is 1 byte/word length, and so on. write to buffer is a multi-cycle operation, where a byte/word count of n + 1 is written to the correct memory address (wa) with the proper data (wd). the confirm command (d0h) is expected after exactly n + 1 write cycles; any other command at that point in the sequence aborts the buffered write. writing a byte/word count outside the buffer boundary causes unexpected results and should be avoided. 10. the write to buffer, block erase, or full chip erase operation does not begin until a confirm command (d0h) is issued. confirm also reactivates suspended operations. 11. a block lock-bit can be set only while wp# is v ih . 12. wp# must be at v ih to clear block lock-bits. the clear block lock-bits operation simultaneously clears all block lock-bits. 13. commands other than those shown above are reserved for future use and should not be used. 14. the basic command set (bcs) is the same as the 28f008sa command set or intel standard command set. the scaleable command set (scs) is also referred to as the intel extended command set.
28f160s5, 28f320s5 e 16 advance information 4.1 read array command upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. this operation is also initiated by writing the read array command. the device remains enabled for reads until another command is written. once the internal wsm has started block erase, program, or lock-bit configuration, the device will not recognize the read array command until the wsm completes its operation unless the wsm is suspended via an erase-suspend or program- suspend command. the read array command functions independently of the v pp voltage. 4.2 read query mode command this section defines the data structure or database returned by the common flash interface (cfi) query command. system software should parse this structure to gain critical information such as block size, density, x8/x16, and electrical specifications. once this information has been obtained, the software will know which command sets to use to enable flash writes, block erases, and otherwise control the flash component. the query is part of an overall specification for multiple command set and control interface descriptions called common flash interface, or cfi. 4.2.1 query structure output the query database allows system software to gain critical information for controlling the flash component. this section describes the devices cfi-compliant interface that allows the host system to access query data. query data are always presented on the lowest- order data outputs (dq 0-7 ) only. the numerical offset value is the address relative to the maximum bus width supported by the device. on this device, the query table device starting address is a 10h word address, since the maximum bus width is x16. for this word-wide (x16) device, the first two bytes of the query structure, q and r in ascii, appear on the low byte at word addresses 10h and 11h. this cfi-compliant device outputs 00h data on upper bytes. thus, the device outputs ascii q in the low byte (dq 0-7 ) and 00h in the high byte (dq 8-15 ). since the device is x8/x16 capable, the x8 data is still presented in word-relative (16-bit) addresses. however, the fill data (00h) is not the same as driven by the upper bytes in the x16 mode. as in x16 mode, the byte address (a 0 ) is ignored for query output so that the odd byte address (a 0 high) repeats the even byte address data (a 0 low). therefore, in x8 mode using byte addressing, the device will output the sequence q, q, r, r, y, y, and so on, beginning at byte-relative address 20h (which is equivalent to word offset 10h in x16 mode). at query addresses containing two or more bytes of information, the least significant data byte is presented at the lower address, and the most significant data byte is presented at the higher address.
e 28f160s5, 28f320s5 17 advance information table 4. summary of query structure output as a function of device and mode device type/mode word addressing byte addressing location quer y data hex, ascii location quer y data hex, ascii x16 device/ x16 mode 10h 11h 12h 0051h q 0052h r 0059h y 20h 21h 22h 51h q 00h null 52h r x16 device/ x8 mode n/a (1) n/a 20h 21h 22h 51h q 51h q 52h r note: 1. the system must drive the lowest order addresses to access all the devices array data when the device is configured in x8 mode. therefore, word addressing where lower addresses are not toggled by the system is not applicable for x8- configured devices. table 5. example of query structure output of a x16- and x8-capable device device address word addressin g : query data b y te address byte addressing: query data a 16 Ca 1 d 15 Cd 0 a 7 Ca 0 d 7 Cd 0 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h ... 0051h q 0052h r 0059h y p_id lo prvendor p_id hi id # p lo prvendor p hi tbladr a_id lo altvendor a_id hi id # ... 20h 21h 22h 23h 24h 25h 26h 27h 28h ... 51h q 51h q 52h r 52h r 59h y 59h y p_id lo prvendor p_id lo id # p_id hi ...
28f160s5, 28f320s5 e 18 advance information 4.2.2 query structure overview the query command causes the flash component to display the common flash interface (cfi) query structure or database. the structure sub-sections and address locations are summarized in table 8. the following sections describe the query structure sub-sections in detail. table 6. query structure (1) offset sub-section name description 00h manufacturer code 01h device code (ba+2)h (2) block status register block-specific information 04-0fh reserved reserved for vendor-specific information 10h cfi query identification string command set id and vendor data offset 1bh system interface information device timing & voltage information 27h device geometry definition flash device layout p (3) primary intel-specific extended query table vendor-defined additional information specific to the primary vendor algorithm notes: 1. refer to section 4.2.1 and table 4 for the detailed definition of offset address as a function of device word width and mode . 2. ba = the beginning location of a block address (i.e., 08000h is the beginning location of block 1 when the block size is 32 kword). 3. offset 15 defines p which points to the primary intel-specific extended query table.
e 28f160s5, 28f320s5 19 advance information 4.2.3 block status register the block status register indicates whether an erase operation completed successfully or whether a given block is locked or can be accessed for flash program/erase operations. block erase status (bsr.1) allows system software to determine the success of the last block erase operation. bsr.1 can be used just after power-up to verify that the v cc supply was not accidentally removed during an erase operation. this bit is only reset by issuing another erase operation to the block. the block status register is accessed from word address 02h within each block. table 7. block status register offset len g th (bytes) description 28f32/160s5 x16 device/mode (ba+2)h (1) 01h block status register ba+2: 0000h or 0001h bsr.0 = block lock status 1 = locked 0 = unlocked ba+2 (bit 0): 0 or 1 bsr.1 = block erase status 1 = last erase operation did not complete successfully 0 = last erase operation completed successfully ba+2 (bit 1): 0 or 1 bsr 2-7 reserved for future use ba+2 (bits 2-7): 0 note: 1. ba = the beginning location of a block address (i.e., 008000h is the beginning location of block 1 in word mode.)
28f160s5, 28f320s5 e 20 advance information 4.2.4 cfi query identification string the identification string provides verification that the component supports the common flash interface specification. additionally, it indicates which version of the spec and which vendor- specified command set(s) is (are) supported. table 8. cfi identification offset len g th (bytes) description 28f32/160s5 10h 03h query-unique ascii string qry 10: 0051h 11: 0052h 12: 0059h 13h 02h primary vendor command set and control interface id code 16-bit id code for vendor-specified algorithms 13: 0001h 14: 0000h 15h 02h address for primary algorithm extended query table offset value = p = 31h 15: 0031h 16: 0000h 17h 02h alternate vendor command set and control interface id code second vendor-specified algorithm supported note: 0000h means none exists 17: 0000h 18: 0000h 19h 02h address for secondary algorithm extended query table note: 0000h means none exists 19: 0000h 1a: 0000h
e 28f160s5, 28f320s5 21 advance information 4.2.5 system interface information the following device information can be useful in optimizing system interface software. table 9. system interface information offset len g th (bytes) description 28f32/160s5 1bh 01h v cc logic supply minimum program/erase voltage bits 7 C4 bcd volts bits 3C0 bcd 100 mv 1b: 0030h 1ch 01h v cc logic supply maximum program/erase voltage bits 7C4 bcd volts bits 3C0 bcd 100 mv 1c: 0055h 1dh 01h v pp [programming] supply minimum program/erase voltage bits 7C4 hex volts bits 3C0 bcd 100 mv 1d: 0030h 1eh 01h v pp [programming] supply maximum program/erase voltage bits 7C4 hex volts bits 3C0 bcd 100 mv 1e: 0055h 1fh 01h typical time-out per single byte/word program, 2 n - sec 1f: 0003h 20h 01h typical time-out for max. buffer write, 2 n -sec 20: 0006h 21h 01h typical time-out per individual block erase, 2 n m-sec 21: 000ah 22h 01h typical time-out for full chip erase, 2 n m-sec 22: 000fh 23h 01h maximum time-out for byte/word program, 2 n times typical 23: tbd 24h 01h maximum time-out for buffer write, 2 n times typical 24: tbd 25h 01h maximum time-out per individual block erase, 2 n times typical 25: tbd 26h 01h maximum time-out for chip erase, 2 n times typical 26: tbd
28f160s5, 28f320s5 e 22 advance information 4.2.6 device geometry definition this field provides critical details of the flash device geometry. table 10. device geometry definition offset len g th (bytes) description 28f32/160s5 27h 01h device size = 2 n in number of bytes 27: 0015h (16 mbit) 27: 0016h (32 mbit) 28h 02h flash device interface description value meaning 0002h x8/x16 asynchronous 28: 0002h 29: 0000h 2ah 02h maximum number of bytes in write buffer = 2 n 2a: 0005h 2b: 0000h 2ch 01h number of erase block regions within device: bits 7 C0 = x = # of erase block regions 2c: 0001h 2dh 04h erase block region information bits 15C0 = y , where y+1 = number of erase blocks of identical size within region bits 31C16 = z , where the erase block(s) within this region are (z) 256 bytes y: 32 blocks (16 mbit) 2d: 001fh 2e: 0000h y: 64 blocks (32 mbit) 2d: 003fh 2e: 0000h z: (64-kb) 2f: 0000h 30: 0001h
e 28f160s5, 28f320s5 23 advance information 4.2.7 intel-specific extended query table certain flash features and commands are optional. the intel-specific extended query table specifies this and other similar types of information. table 11. primary-vendor specific extended query offset (1) len g th (bytes) description data (p)h 03h primary extended query table unique ascii string pri 31: 0050h 32: 0052h 33: 0049h (p+3)h 01h major version number, ascii 34: 0031h (p+4)h 01h minor version number, ascii 35: 0030h (p+5)h 04h optional feature & command support bit 0 chip erase supported ( 1=yes , 0=no) bit 1 suspend erase supported ( 1=yes , 0=no) bit 2 suspend program supported ( 1=yes , 0=no) bit 3 lock/unlock supported ( 1=yes , 0=no) bit 4 queued erase supported (1=yes, 0=no ) bits 5 C31 reserved for future use; undefined bits are 0 36: 000fh 37: 0000h 38: 0000h 39: 0000h (p+9)h 01h supported functions after suspend read array, status, and query are always supported during suspended erase or program operation. this field defines other operations supported. bit 0 program supported after erase suspend ( 1=yes , 0=no) bits 1-7 reserved for future use; undefined bits are 0 3a: 0001h (p+a)h 02h block status register mask defines which bits in the block status register section of query are implemented. bit 0 block status register lock-bit [bsr.0] active ( 1=yes , 0=no) bit 1 block erase status bit [bsr.1] active ( 1=yes , 0=no) bits 2-15 reserved for future use; undefined bits are 0 3b: 0003h 3c: 0000h notes: 1. the variable p is a pointer which is defined at offset 15h in table 8.
28f160s5, 28f320s5 e 24 advance information table 11. primary-vendor specific extended query (continued) offset len g th (bytes) description data (p+c)h 01h v cc logic supply optimum program/erase voltage (highest performance) bits 7 C4 bcd value in volts bits 3C0 bcd value in 100 mv 3d: 0050h (p+d)h 01h v pp [programming] supply optimum program/erase voltage bits 7C4 hex value in volts bits 3C0 bcd value in 100 mv 3e: 0050h (p+e)h reserved reserved for future use table 12. identifier codes code address (2) data manufacturer code 000000 b0 device code 16 mbit 000001 d0 32 mbit 000001 d4 block lock configuration x 0002 (1) block is unlocked dq 0 = 0 block is locked dq 0 = 1 reserved for future use dq 2-7 block erase status x0002 (1) last erase completed successfully dq 1 = 0 last erase did not complete successfully dq 1 = 1 reserved for future use dq 2-7 notes: 1. x selects the specific block lock configuration code. see figure 5 for the device identifier code memory map. 2. a 0 should be ignored in this address. the lowest order address line is a 1 in both word and byte mode. 4.3 read identifier codes command the identifier code operation is initiated by writing the read identifier codes command. following the command write, read cycles from addresses shown in figure 5 retrieve the manufacturer, device, block lock configuration, and block erase status codes (see table 12 for identifier code values). to terminate the operation, write another valid command. like the read array command, the read identifier codes command functions independently of the v pp voltage. following the read identifier codes command, the information in table 12 can be read. 4.4 read status register command the status register may be read to determine when programming, block erasure, or lock-bit configuration is complete and whether the operation completed successfully. it may be read at any time by writing the read status register command. after writing this command, all subsequent read operations output data from the status register until another valid command is written. the status register contents are latched on the falling edge of oe#, ce 0 #, or ce 1 # whichever occurs last. oe# or ce x # must toggle to v ih to update the status register latch. the read status register command functions independently of the v pp voltage.
e 28f160s5, 28f320s5 25 advance information following a program, block erase, set block lock-bit, or clear block lock-bits command sequence, only sr.7 is valid until the write state machine completes or suspends the operation. device i/o pins dq 0-6 and dq 8-15 are invalid. when the operation completes or suspends (sr.7 = 1), all contents of the status register are valid when read. the extended status register (xsr) may be read to determine write buffer availability (see table 16). the xsr may be read at any time by writing the write to buffer command. after writing this command, all subsequent read operations output data from the xsr, until another valid command is written. the contents of the xsr are latched on the falling edge of oe# or ce x # whichever occurs last in the read cycle. write to buffer comm and must be re-issued to update the xsr latch. 4.5 clear status register command status register bits sr.5, sr.4, sr.3, and sr.1 are set to 1s by the wsm and can only be reset by the clear status register command. these bits indicate various failure conditions (see table 15). by allowing system software to reset these bits, several operations (such as cumulatively erasing or locking multiple blocks or programming several bytes/words in sequence) may be performed. the status register may be polled to determine if an error occurred during the sequence. to clear the status register, the clear status register command is written. it functions independently of the applied v pp voltage. this command is not functional during block erase or program suspend modes. 4.6 block erase command block erase is executed one block at a time and initiated by a two-cycle comm and. a block erase setup command is written first, followed by a confirm command. this command sequence requires appropriate sequencing and an address within the block to be erased (erase changes all block data to ffh). block preconditioning, erase, and verify are handled internally by the wsm (invisible to the system). after the two-cycle block erase sequence is written, the device automatically outputs status register data when read (see figure 9). the cpu can detect block erase completion by analyzing sts in level ry/by# mode or status register bit sr.7. toggle oe#, ce 0 #, or ce 1 # to update the status register. when the block erase is complete, status register bit sr.5 should be checked. if a block erase error is detected, the status register should be cleared before system software attempts corrective actions. the cui remains in read status register mode until a new command is issued. this two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. an invalid block erase command sequence will result in both status register bits sr.4 and sr.5 being set to 1. also, reliable block erasure can only occur when v cc = v cc1/2 and v pp = v pph . in the absence of these voltages, block contents are protected against erasure. if block erase is attempted while v pp v pplk , sr.3 and sr.5 will be set to 1. successful block erase requires that the corresponding block lock-bit be cleared, or wp# = v ih . if block erase is attempted when the corresponding block lock-bit is set and wp# = v il, the block erase will fail and sr.1 and sr.5 will be set to 1. 4.7 full chip erase command the full chip erase command followed by a confirm command erases all unlocked blo cks. after the confirm command is written, the device erases all unlocked blocks from block 0 to block 31 (or 63) sequentially. block preconditioning, erase, and verify are handled internally by the wsm. after the full chip erase command sequence is written to the cui, the device automatically outputs the status register data when read. the cpu can detect full chip erase completion by polling the sts pin in level ry/by# mode or status register bit sr.7. when the full chip erase is complete, status register bit sr.5 should be checked to see if the operation completed successfully. if an erase error occurred, the status register should be cleared before issuing the next command. the cui remains in read status register mode until a new command is issued. if an error is detected while erasing a block during a full chip erase operation, the wsm skips the remaining cells in that block and proceeds to erase the next block. reading the block valid status code by issuing the read identifier codes command or query command informs the user of which block(s) failed to erase.
28f160s5, 28f320s5 e 26 advance information this two-step command sequence of setup followed by execution ensures that block contents are not accidentally erased. an invalid full chip erase command sequence will result in both status register bits sr.4 and sr.5 being set to 1. also, reliable full chip erasure can only occur when v cc = v cc1/2 and v pp = v pph . in the absence these voltages, block contents are protected against erasure. if full chip erase is attempted while v pp v pplk , sr.3 and sr.5 will be set to 1. when wp# = v il , only unlocked blocks are erased. full chip erase cannot be suspended. 4.8 write to buffer command to program the flash device via the write buffers, a write to buffer command sequence is initiated. a variable number of bytes or words, up to the buffer size, can be written into the buffer and programmed to the flash device. first, the write to buffer setup command is issued along with the block address. at this point, the extended status register information is loaded and xsr.7 reverts to the buffer available status. if xsr.7 = 0, no write buffer is available. to retry, continue monitoring xsr.7 by issuing the write to buffer setup command with the block address until xsr.7 = 1. when xsr.7 transitions to a 1, the buffer is ready for loading. now a word/byte count is issued at an address within the block. on the next write, a device start address is given along with the write buffer data. for maximum programming performance and lower power, align the start address at the beginning of a write buffer boundary. subsequent writes must supply additional device addresses and data, depending on the count. all subsequent addresses must lie within the start address plus the count. after the final buffer data is given, a write confirm command is issued. this initiates the wsm to begin copying the buffer data to the flash memory. if a command other than write confirm is written to the device, an invalid command/sequence error will be generated and status register bits sr.5 and sr.4 will be set to 1. for additional buffer writes, issue another write to buffer setup command and check xsr.7. the write buffers can be loaded while the wsm is busy as long as xsr.7 indicates that a buffer is available. refer to figure 6 for the write to buffer flowchart. if an error occurs while writing, the device will stop programming, and status register bit sr.4 will be set to a 1 to indicate a program failure. any time a media failure occurs during a program or an erase (sr.4 or sr.5 is set), the device will not accept any more write to buffer commands. additionally, if the user attempts to write past an erase block boundary with a write to buffer command, the device will abort programming. this will generate an invalid command/sequence error and status register bits sr.5 and sr.4 will be set to 1. to clear sr.4 and/or sr.5, issue a clear status register command. reliable buffered programming can only occur when v cc = v cc1/2 and v pp = v pph . if programming is attempted while v pp v pplk , status register bits sr.4 and sr.5 will be set to 1. programming attempts with invalid v cc and v pp voltages produce spurious results and should not be attempted. finally, successful programming requires that the corresponding block lock-bit be cleared, or wp# = v ih . if a buffered write is attempted when the corresponding block lock-bit is set and wp# = v il , sr.1 and sr.4 will be set to 1. 4.9 byte/word program command byte/word programming is executed by a two-cycle command sequence. byte/word program setup (standard 40h or alternate 10h) is written, followed by a second write that specifies the address and data (latched on the rising edge of we#). the wsm then takes over, controlling the program and verify algorithms internally. after the write sequence is written, the device automatically outputs status register data when read. the cpu can detect the completion of the program event by analyzing sts in level ry/by# mode or status register bit sr.7. when programming is complete, status register bit sr.4 should be checked. if a programming error is detected, the status register should be cleared. the internal wsm verify only detects errors for 1s that do not successfully program to 0s. the cui remains in read status register mode until it receives another command. refer to figure 7 for the word/byte program flowchart. also, reliable byte/word programming can only occur when v cc = v cc1/2 and v pp = v pph . in the absence of this high voltage, contents are protected against programming. if a byte/word program is
e 28f160s5, 28f320s5 27 advance information attempted while v pp v pplk , status register bits sr.4 and sr.3 will be set to 1. successful byte/word programming requires that the corresponding block lock-bit be cleared. if a byte/word program is attempted when the corresponding block lock-bit is set and wp# = v il , sr.1 and sr.4 will be set to 1. 4.10 sts configuration command the status (sts) pin can be configured to different states using the sts pin configuration command. once the sts pin has been configured, it remains in that configuration until another configuration command is issued or rp# is low. initially, the sts pin defaults to level ry/by# operation where sts low indicates that the state machine is busy. sts high indicates that the state machine is ready for a new operation or suspended. to reconfigure the status (sts) pin to other modes, the sts pin configuration command is issued followed by the desired configuration code. the three alternate configurations are all pulse mode for use as a system interrupt as descri bed in table 14. for these configurations, bit 0 controls erase complete interrupt pulse, and bit 1 controls write complete interrupt pulse. when the device is configured in one of the pulse modes, the sts pin pulses low with a typical pulse width of 250 ns. supplying the 00h configuration code with the configuration command resets the sts pin to the default ry/by# level mode. refer to table 14 for configuration coding definitions. the configuration command may only be given when the device is not busy or suspended. check sr.7 for device status. an invalid configuration code will result in both status register bits sr.4 and sr.5 being set to 1. 4.11 block erase suspend command the block erase suspend command allows block-erase interruption to read or program data in another block of memory. once the block erase process starts, writing the block erase suspend command requests that the wsm suspend the block erase sequence at a predetermined point in the algorithm. the device outputs status register data when read after the block erase suspend command is written. polling status register bits sr.7 can determine when the block erase operation has been suspended. when sr.7 = 1, sr.6 should also be set to 1, indicating that the device is in the erase suspend mode. sts in level ry/by# mode will also transition to v oh . specification t whrh2 defines the block erase suspend latency. at this point, a read array command can be written to read data from blo cks other t han that which is suspended. a program command sequence can also be issued during erase suspend to program data in other blocks. using the program sus pend command (see section 4.12), a program operation can also be suspended. during a program operation with block erase suspended, status register bit sr.7 will return to 0 and sts in ry/by# mode will transition to v ol . however, sr.6 will remain 1 to indicate block erase suspend status. the only other valid commands while block erase is suspended are read status register and block erase resume. after a block erase resume command is written to the flash memory, the wsm will continue the block erase process. status register bits sr.6 and sr.7 will automatically clear and sts in ry/by# mode will return to v ol . after the erase resume command is written, the device automatically outputs status register data when read (see figure 10). v pp must remain at v pph and v cc must remain at v cc1/2 (the same v pp and v cc levels used for block erase) while block erase is suspended. rp# must also remain at v ih (the same rp# level used for block erase). block erase cannot resume until program operations initiated during block erase suspend have completed. 4.12 program suspend command the program suspend command allows program interruption to read data in other flash memory locations. once the programming process starts, writing the program suspend command requests that the wsm suspend the program sequence at a predetermined point in the algorithm. the device continues to output status register data when read after the program suspend command is written. polling status register bits sr.7 can determine when the programming operation has been suspended. when sr.7 = 1, sr.2 should also be set to 1, indicating that the device is in the program suspend mode. sts in level ry/by# mode will also transition to v oh . specification t whrh1 defines the program suspend latency. at this point, a read array command can be written to read data from locations other than that which is
28f160s5, 28f320s5 e 28 advance information suspended. the only other valid commands while programming is suspended are read status register and program resume. after a program resume command is written, the wsm will continue the programming process. status register bits sr.2 and sr.7 will automatically clear and sts in ry/by# mode will return to v ol . after the program resume command is written, the device automatically outputs status register data when read. v pp must remain at v pph and v cc must remain at v cc1/2 (the same v pp and v cc levels used for programming) while in program suspend mode. rp# must also remain at v ih (the same rp# level used for programming). refer to figure 8 for the program suspend/resume flowchart. 4.13 set block lock-bit command a flexible block locking and unlocking scheme is enabled via a combination of block lock-bits. the block lock-bits gate program and erase operations. with wp# = v ih , individual block lock-bits can be set using the set block lock-bit command. set block lock-bit is initiated using a two-cycle command sequence. the set block lock-bit setup along with appropriate block or device address is written followed by the set block lock-bit confirm and an address within the block to be locked. the wsm then controls the set lock-bit algorithm. after the sequence is written, the device automatically outputs status register data when read. the cpu can detect the completion of the set lock-bit event by analyzing sts in level ry/by# mode or status register bit sr.7. when the set lock-bit operation is complete, status register bit sr.4 should be checked. if an error is detected, the status register should be cleared. the cui will remain in read status register mode until a new command is issued. this two-step sequence of setup followed by execution ensures that lock-bits are not accidentally set. an invalid set block lock-bit command will result in status register bits sr.4 and sr.5 being set to 1. also, reliable operations occur only when v cc = v cc1/2 and v pp = v pph . in the absence these voltages, lock-bit contents are protected against alteration. a successful set block lock-bit operation requires that wp# = v ih . if it is attempted with wp# = v il , the operation will fail and sr.1 and sr.4 will be set to 1. see table 13 for write protection alternatives. refer to figure 11 for the set block lock-bit flowchart. 4.14 clear block lock-bits command all set block lock-bits are cleared in parallel via the clear block lock-bits command. this command is valid only when wp# = v ih . the clear block lock-bits operation is initiated using a two-cycle comm and sequence. a clear block lock-bits setup command is written followed by a confirm command. then, the device automatically outputs status register data when read (see figure 12). the cpu can detect completion of the clear block lock-bits event by analyzing sts in level ry/by# mode or status register bit sr.7. this two-step sequence of set-up followed by execution ensures that block lock-bits are not accidentally cleared. an invalid clear block lock-bits command sequence will result in status register bits sr.4 and sr.5 being set to 1. also, a reliable clear block lock-bits operation can only occur when v cc = v cc1/2 and v pp = v pph . if a clear block lock-bits operation is attempted while v pp v pplk , sr.3 and sr.5 will be set to 1. in the absence of these voltages, the block lock-bits contents are protected against alteration. a successful clear block lock-bits operation requires that wp# = v ih . if a clear block lock-bits operation is aborted due to v pp or v cc transitioning out of valid range or rp# or wp# active transition, block lock-bit values are left in an undetermined state. a repeat of clear block lock-bits is required to initialize block lock-bit contents to known values. when the operation is complete, status register bit sr.5 should be checked. if a clear block lock-bit error is detected, the status register should be cleared. the cui will remain in read status register mode until another command is issued.
e 28f160s5, 28f320s5 29 advance information table 13. write protection alternatives operation bloc k lock- bit wp# effect program and 0 v il or v ih block erase and programming enabled block erase 1 v il block is locked. block erase and programming disabled v ih block lock-bit override. block erase and programming enabled full chip erase 0,1 v il all unlocked blocks are erased xv ih block lock-bit override. all blocks are erased set or clear x v il set or clear block lock-bit disabled block lock-bit v ih set or clear block lock-bit enabled table 14. configuration coding definitions reserved pulse on write complete pulse on erase complete bits 7 C2 bit 1 bit 0 dq7 Cdq2 = reserved dq1/dq0 = sts pin configuration codes 00 = default, level mode ry/by# (device ready) indication 01 = pulse on erase complete 10 = pulse on flash program complete 11 = pulse on erase or program complete configuration codes 01b, 10b, and 11b are all pulse mode such that the sts pin pulses low then high when the operation indicated by the given configuration is completed. configuration command sequences for sts pin configuration (masking bits d7Cd2 to 00h) are as follows: default ry/by# level mode b8h, 00h er int (erase interrupt): b8h, 01h pulse-on-erase complete pr int (program interrupt): b8h, 02h pulse-on-flash-program complete er/pr int (erase or program interrupt): b8h, 03h pulse-on-erase or program complete dq7Cdq2 are reserved for future use. default (dq1/dq0 = 00) ry/by#, level mode ----- used to control hold to a memory controller to prevent accessing a flash memory subsystem while any flash device's wsm is busy. configuration 01 er int, pulse mode (1) ----- used to generate a system interrupt pulse when any flash device in an array has completed a block erase or sequence of queued block erases. helpful for reformatting blocks after file system free space reclamation or cleanup configuration 10 pr int, pulse mode (1) ----- used to generate a system interrupt pulse when any flash device in an array has complete a program operation. provides highest performance for servicing continuous buffer write operations. configuration er/pr int, pulse mode (1) ----- used to generate system interrupts to trigger servicing of flash arrays when either erase or flash program operations are completed when a common interrupt service routine is desired. note: 1. when the device is configured in one of the pulse modes, the sts pin pulses low with a typical pulse width of 250 ns.
28f160s5, 28f320s5 e 30 advance information table 15. status register definition wsms ess eclbs bwslbs vpps bwss dps r 765 4 3210 notes: sr.7 = write state machine status 1 = ready 0 = busy check sts in ry/by# mode or sr.7 to determine block erase, programming, or lock-bit configuration completion. sr.6-0 are invalid while sr.7 = 0. sr.6 = erase suspend status 1 = block erase suspended 0 = block erase in progress/completed sr.5 = erase and clear lock-bits status 1 = error in block erasure or clear lock-bits 0 = successful block erase or clear lock-bits if both sr.5 and sr.4 are 1s after a block erase or lock-bit configuration attempt, an improper command sequence was entered. sr.4 = program and set lock-bit status 1 = error in program or block lock-bit 0 = successful program or set block lock-bit sr.3 = v pp status 1 = v pp low detect, operation abort 0 = v pp ok sr.3 does not provide a continuous indication of v pp level. the wsm interrogates and indicates the v pp level only after a block erase, program, or lock- bit configuration operation. sr.3 reports accurate feedback only when v pp = v pph . sr.2 = program suspend status 1 = program suspended 0 = program in progress/completed sr.1 = device protect status 1 = block lock-bit and/or rp# lock detected, operation abort 0 = unlock sr.1 does not provide a continuous indication of block lock-bit values. the wsm interrogates the block lock-bit, and wp# only after a block erase, program, or lock-bit configuration operation. it informs the system, depending on the attempted operation, if the block lock-bit is set. sr.0 = reserved for future enhancements sr.0 is reserved for future use and should be masked when polling the status register. table 16. extended status register definition wbs r r r r r r r 765 4 3210 notes: xsr.7 = write buffer status 1 = write to buffer available 0 = write to buffer not available after a write to buffer command, xsr.7 indicates that another write to buffer command is possible. xsr.6 = reserved for future enhancements sr.6C0 are reserved for future use and should be masked when polling the status register
e 28f160s5, 28f320s5 31 advance information bus o p eration command comments write write to buffer data = e8h addr = block address read xsr.7=valid addr = x standby check xsr.7 1 = write buffer available 0 = write buffer not available write ( note 1 , 2 ) data = n = word/byte count n = 0 corresponds to count = 1 addr = block address write ( note 3 , 4 ) data = write buffer data addr = device start address write ( note 5 , 6 ) data = write buffer data addr = device address write buffer write to flash confirm data = d0h addr = x read status register data ce# & oe# low updates sr addr = x standby check sr.7 1 = wsm ready 0 = wsm busy 1. byte- or word-count values on dq 0-7 are loaded into the count register. 2. the device now outputs the status register when read (xsr is no longer available). 3. write buffer contents will be programmed at the device start address or destination flash address. 4. align the start address on a write buffer boundary for maximum programming performance. 5. the device aborts the write to buffer command if the current address is outside of the original block address. 6. the status register indicates an improper command sequence if the write to buffer command is aborted. follow this with a clear status register command. full status check can be done after all erase and write sequences complete. write ffh after the last operation to reset the device to read array mode. start write word or byte count, block address write buffer data, start address x = 0 x = x + 1 write next buffer data, device address abort buffer write command? x = n another buffer write? read status register sr.7 = buffer write to flash complete read extended status register xsr.7 = 1 no yes no no 1 buffer write to flash aborted yes no yes full status check if desired buffer write to flash confirm d0h issue write command e8h, block address write to another block address write buffer time-out? 0 yes suspend write? yes suspend write loop set time-out issue read status command no 0 0608_07 figure 6. write to buffer flowchart
28f160s5, 28f320s5 e 32 advance information 0608_08 figure 7. single byte/word program flowchart
e 28f160s5, 28f320s5 33 advance information 0608_09 figure 8. program suspend/resume flowchart
28f160s5, 28f320s5 e 34 advance information bus o p eration command comments write erase block data = 28h or 20h addr = block address read xsr.7=valid addr = x standby check xsr.7 1 = erase queue available 0 = no erase queue available write erase block data = 28h addr = block address read sr.7=valid; sr.6-0=x with the device enabled, oe# low updates sr addr = x standby check xsr.7 1 = erase queue available 0 = no erase queue available write (note 1) erase confirm data = d0h addr = x read status register data with the device enabled, oe# low updates sr addr = x standby check sr.7 1 = wsm ready 0 = wsm busy 1. the erase confirm b y te must follow erase setup when the erase queue status (xsr.7)=0. full status check can be done after all erase and write sequences complete. write ffh after the last operation to reset the device to read array mode. erase block time-out? start read status register sr.7 = erase flash block(s) complete 0 1 no full status check if desired suspend erase no yes device supports queuing issue block queue erase command 28h, block address read extended status register is queue available? xsr.7= another block erase? issue erase command 28h block address read extended status register write confirm d0h block address another block erase? is queue full? xsr.7= 0=yes 1=no yes no 1=yes yes issue single block erase command 20h, block address no 0=no no suspend erase loop yes yes write confirm d0h block address set time-out issue read status command queued erase section (include this section for compatibility with future scs-compliant devices) 0609_10 figure 9. block erase flowchart
e 28f160s5, 28f320s5 35 advance information sr.7 = 0 1 start write b0h read status register write d0h block erase resumed bus operation command comments write erase suspend read data = b0h addr = x check sr.7 1 = wsm ready 0 = wsm busy status register data addr = x standby sr.6 = block erase completed write ffh read array data 0 1 check sr.6 1 = block erase suspended 0 = block erase completed standby data = d0h addr = x write erase resume read array data write loop read or write? write read done? yes no figure 10. block erase suspend/resume flowchart
28f160s5, 28f320s5 e 36 advance information sr.7 = 0 1 start write 60h, block/device address write 01h/f1h, block/device address full status check if desired set lock-bit complete full status check procedure 1 0 read status register data (see above) 1 0 read status register voltage range error bus operation command comments standby standby sr.5, sr.4, sr.3 and sr.1 are only cleared by the clear status register command in cases where multiple lock-bits are set before full status is checked. if error is detected, clear the status register before attempting retry or other error recovery. bus operation command comments write write set block/master lock-bit setup data = 01h (block), f1h (master) addr = block address (block), device address (master) read data = 60h addr = block address (block), device address (master) check sr.7 1 = wsm ready 0 = wsm busy repeat for subsequent lock-bit set operations. full status check can be done after each lock-bit set operation or after a sequence of lock-bit set operations. write ffh after the last lock-bit set operation to place device in read array mode. standby sr.3 = sr.4 = set lock-bit error set lock-bit successful set block or master lock-bit confirm status register data standby check sr.4 1 = set lock-bit error 0 1 device protect error sr.1 = 1 0 sr.4,5 = command sequence error check sr.4,5 both 1 = command sequence error standby check sr.1 1 = device protect detect rst# = v (set master lock-bit operation) rst# = v , master lock-bit is set (set block lock-bit operation) ih ih check sr.3 1 = programming voltage error detect figure 11. set block lock-bit flowchart
e 28f160s5, 28f320s5 37 advance information sr.7 = 0 1 start write 60h write d0h full status check if desired clear block lock-bits complete full status check procedure 1 0 read status register data (see above) 1 0 read status register voltage range error 1 0 command sequence error sr.3 = sr.5 = sr.4,5 = clear block lock-bits error bus operation command comments standby check sr.4,5 both 1 = command sequence error standby sr.5, sr.4, sr.3 and sr.1 are only cleared by the clear status register command. if error is detected, clear the status register before attempting retry or other error recovery. check sr.5 1 = clear block lock-bits error standby bus operation command comments write write clear block lock-bits setup read data = 60h addr = x check sr.7 1 = wsm ready 0 = wsm busy write ffh after the clear block lock-bits operation to place device to read array mode. status register data standby clear block lock-bits confirm data = d0h addr = x clear block lock-bits successful standby 0 1 device protect error sr.1= check sr.3 1 = programming voltage error detect check sr.1 1 = device protect detect rst# = v , master lock-bit is set ih figure 12. clear block lock-bits flowchart
28f160s5, 28f320s5 e 38 advance information 5.0 design considerations 5.1 three-line output control intel provides three control inputs to accommodate multiple memory connections: ce x # (ce 0 #, ce 1 #), oe#, and rp#. three-line control provides for: a. lowest possible memory power dissipation; b. data bus contention avoidance. to use these control inputs efficiently, an address decoder should enable cex# while oe# should be connected to all memory devices and the systems read# control line. this assures that only selected memory devices have active outputs, while de- selected memory devices are in standby mode. rp# should be connected to the system powergood signal to prevent unintended writes during system power transitions. powergood should also toggle during system reset. 5.2 sts and wsm polling sts is an open drain output that should be connected to v cc by a pull-up resistor to provide a hardware form of detecting block erase, program, and lock-bit configuration completion. in default mode, it transitions low during execution of these commands and returns to v oh when the wsm has finished executing the internal algorithm. for alternate sts pin configurations, see section 4.10. sts can be connected to an interrupt input of the system cpu or controller. it is active at all times. sts, in default mode, is also v oh when the device is in block erase suspend (with programming inactive) or in reset/power-down mode. 5.3 power supply decoupling flash memory power switching characteristics require careful device decoupling. standby current levels, active current levels and transient peaks produced by falling and rising edges of ce x # and oe# are areas of interest. two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. each device should have a 0.1 f ceramic capacitor connected between its v cc and gnd and v pp and gnd. these high- frequency, low-inductance capacitors should be placed as close as possible to package leads. additionally, for every eight devices, a 4.7 f electrolytic capacitor should be placed at the arrays power supply connection between v cc and gnd. the bulk capacitor will overcome voltage slumps caused by pc board trace inductance. 5.4 v pp trace on printed circuit boards updating target- system resi dent flash memories requires that the printed circuit board designer pay attention to v pp power supply traces. the v pp pin supplies the memory cell current for programming and block erasing. use similar trace widths and layout considerations given to the v cc power bus. adequate v pp supply traces and decoupling will decrease v pp voltage spikes and overshoots. 5.5 v cc , v pp , rp# transitions block erase, program, and lock-bit configuration are not guaranteed if rp# 1 v ih, or if v pp or v cc fall outside of a valid voltage range (v cc1/2 and v pph ). if v pp error is detected, status register bit sr.3 and sr.4 or sr.5 are set to 1. if rp# transitions to v il during block erase, program, or lock-bit configuration, sts in level ry/by# mode will remain low until the reset operation is complete. then, the operation will abort and the device will enter deep power-down. because the aborted operation may leave data partially altered, the command sequence must be repeated after normal operation is restored. 5.6 power-up/down protection the device offers protection against accidental block erase, programming, or lock-bit configuration during power transitions. a system desi gner must guard against spurious writes for v cc voltages above v lko when v pp is active. since both we# and ce x # must be low for a command write, driving either input signal to v ih will inhibit writes. the cuis two-step command sequence architecture provides an added level of protection against data alteration. in-system block lock and unlock renders additional protection during power-up by prohibiting block erase and program operations. rp# = v il disables the device regardless of its control inputs states.
e 28f160s5, 28f320s5 39 advance information 6.0 electrical specifications 6.1 absolute maximum ratings temperature under bias ................ C40c to +85c storage temperature................... C65c to +125c voltage on any pin (except v cc and v pp ) .................................... C0.5v to + v cc +0.5v (1) v cc supply voltage ............ C0.2v to + v cc +0.5v (1) v pp update voltage during block erase, flash write, and lock-bit configuration ........... C0.2v to +7.0v (2) output short circuit current.....................100 ma (3) notice: this datasheet contains information on products in the design phase of development. do not finalize a design with this information. revised information will be published when the product is available. verify with your local intel sales office that you have the latest datasheet before finalizing a design * warning: stressing the device beyond the absolute maximum ratings may cause permanent damage. these are stress ratings only. operation beyond the operating conditions is not recommended and extended exposure beyond the operating conditions may affect device reliability. notes: 1. all specified voltages are with respect to gnd. minimum dc voltage is C0.5v on input/output pins and C0.2v on v cc and v pp pins. during transitions, this level may undershoot to C2.0v for periods <20 ns. maximum dc voltage on input/output pins and v cc is v cc +0.5v which, during transitions, may overshoot to v cc +2.0v for periods <20 ns. 2. maximum dc voltage on v pp may overshoot to +7.0v for periods <20 ns. 3. output shorted for no more than one second. no more than one output shorted at a time. 4. operating temperature is for extended product defined by this specification. 6.2 operating conditions table 17. temperature and v cc operating conditions (1) symbol parameter notes min max unit test condition t a operating temperature -40 +85 c ambient temperature v cc1 v cc supply voltage (5v 5%) 4.75 5.25 v v cc2 v cc supply voltage (5v 10%) 4.50 5.50 v notes: 1. device operations in the v cc voltage ranges not covered in the table produce spurious results and should not be attempted.
28f160s5, 28f320s5 e 40 advance information 6.2.1 capacitance table 18. capacitance (1) , t a = +25c, f = 1 mhz symbol parameter typ max unit condition c in input capacitance 6 8 pf v in = 0.0v c out output capacitance 8 12 pf v out = 0.0v note: 1. sampled, not 100% tested. 6.2.2 ac input/output test conditions test points input output 1.5 3.0 0.0 1.5 ac test inputs are driven at 3.0v for a logic "1" and 0.0v for a logic "0." input timing begins, and output timing ends, at 1.5 v. input rise and fall times (10% to 90%) <10 ns. figure 13. transient input/output reference waveform for v cc = 5.0v 5% (high speed testing configuration) test points input output 2.0 0.8 0.8 2.0 2.4 0.45 ac test inputs are driven at v oh (2.4 v ttl ) for a logic "1" and v ol (0.45 v ttl ) for a logic "0." input timing begins at v ih (2.0 v ttl ) and v il (0.8 v ttl ). output timing ends at v ih and v il . input rise and fall times (10% to 90%) <10 ns. figure 14. transient input/output reference waveform for v cc = 5.0v 10% (standard testing configuration) device under test 1.3v 1n914 c l out r = 3.3 k l w c includes jig capacitance l figure 15. transient equivalent testing load circuit test configuration capacitance loading value test configuration c l (pf) v cc = 5.0v 5% 30 v cc = 5.0v 10% 100
e 28f160s5, 28f320s5 41 advance information 6.2.3 dc characteristics table 19. dc characteristics , t a = C40 o c to +85 o c sym parameter notes typ max unit conditions i li input load current 1 1 m av cc = v cc max v in = v cc or gnd i lo output leakage current 1 10 m av cc = v cc max v out = v cc or gnd i ccs v cc standby current 1,3,6 25 100 m a cmos inputs v cc = v cc max ce x # = rp# = v cc 0.2v 0.4 2 ma ttl inputs v cc = v cc max ce x # = rp# = v ih i ccd v cc deep power-down current 1 20 m a rp# = gnd 0.2v i out (ry/by#) = 0 ma i ccr v cc read current 1,5,6 50 ma cmos inputs v cc = v cc max ce x # = gnd f = 8 mhz, i out = 0 ma 65 ma ttl inputs v cc = v cc max ce x # = v il f = 8 mhz, i out = 0 ma i ccw v cc programming and set lock- bit current 1,7 35 ma v pp = v pph i cce v cc block erase or clear block lock-bits current 1,7 30 ma v pp = v pph i ccws i cces v cc program suspend or block erase suspend current 1,2 10 ma ce x # = v ih i pps i ppr v pp standby or v pp read current 1 2 15 a v pp v cc 10 200 a v pp 3 v cc i ppd v pp deep power-down current 1 0.1 5 a rp# = gnd 0.2v i ppw v pp program or set lock-bit current 1,7 80 ma v pp = v pph i ppe v pp block erase or clear block lock-bits current 1,7 40 ma v pp = v pph i ppws i ppes v pp program suspend or block erase suspend current 1 10 200 a v pp = v pph
28f160s5, 28f320s5 e 42 advance information table 19. dc characteristics (continued) sym parameter notes min max unit conditions v il input low voltage 7 C0.5 0.8 v v ih input high voltage 7 2.0 v cc + 0.5 v v ol output low voltage 3,7 0.45 v v cc = v cc min i ol = 5.8 ma v oh1 output high voltage (ttl) 3,7 2.4 v v cc = v cc min i oh = C2.5 ma v oh2 output high voltage (cmos) 3,7 0.85 v cc vv cc = v cc min i oh = C2.5 ma v cc C 0.4 v v cc = v cc min i oh = C100 a v pplk v pp lockout voltage 4,7 1.5 v v pph v pp voltage 4 4.5 5.5 v v lko v cc lockout voltage 8 2.0 v notes: 1. all currents are in rms unless otherwise noted. typical values at nominal v cc voltage and t a = +25 c. these currents are valid for all product versions (packages and speeds). 2. i ccws and i cces are specified with the device de-selected. if read or programmed while in erase suspend mode, the devices current is the sum of i ccws or i cces and i ccr or i ccw . 3. includes sts in level ry/by# mode. 4. block erase, program, and lock-bit configurations are inhibited when v pp v pplk , and not guaranteed in the range between v pplk (max) and v pph (min), and above v pph (max). 5. automatic power savings (aps) reduces typical i ccr to 1 ma at 5v v cc static operation. 6. cmos inputs are either v cc 0.2v or gnd 0.2v. ttl inputs are either v il or v ih . 7. sampled, not 100% tested. 8. with v cc v lko flash memory writes are inhibited.
e 28f160s5, 28f320s5 43 advance information 6.2.4 ac characteristics - read-only operations table 20. ac read characteristics (1,5) , t a = C40 o c to +85 o c versions (4) 5v 5% v cc -70/-90 (all units in ns unless otherwise noted) 5v 10% v cc -80/-100 -100/-110 # sym parameter notes min max min max min max r1 t avav read/write cycle time 16 mbit 1 70 80 100 32 mbit 1 90 100 110 r2 t avqv address to output delay 16 mbit 1 70 80 100 32 mbit 1 90 100 110 r3 t elqv ce x # to output delay 16 mbit 2 70 80 100 32 mbit 2 90 100 110 r4 t phqv rp# high to output delay 400 400 400 r5 t glqv oe# to output delay 2 30 35 40 r6 t elqx ce x # to output in low z 3 0 0 0 r7 t ehqz ce x # high to output in high z 3 25 30 35 r8 t glqx oe# to output in low z 3 0 0 0 r9 t ghqz oe# high to output in high z 3 10 10 15 r10 t oh output hold from address, ce x #, or oe# change, whichever occurs first 3000 r11 t elfl t elfh ce x # low to byte# high or low 3 5 5 5 r12 t flqv t fhqv byte# to output delay 16 mbit 3 70 80 100 32 mbit 3 90 100 110 r13 t flqz byte# to output in high z 3 25 30 30 notes: 1. see ac input/output reference waveform for maximum allowable input slew rate. 2. oe# may be delayed up to t elqv -t glqv after the falling edge of ce x # without impact on t elqv . 3. sampled, not 100% tested. 4. see ordering information for device speeds (valid operational combinations). 5. see figures 13 through 15 for testing characteristics.
28f160s5, 28f320s5 e 44 advance information note: ce x # is the latter of ce 0 # and ce 1 # low or the first of ce 0 # or ce 1 # high. 0608_17 figure 16. ac waveform for read operations
e 28f160s5, 28f320s5 45 advance information 6.2.5 ac characteristics - write operations table 21. write operations (1,6) , t a = C40c to +85c versions (6) 5v 5% 5v 10% v cc valid for all speeds # sym parameter notes min max unit w1 t phwl ( t phel ) rp# high recovery to we# (ce x # ) going low 2 1 s w2 t elwl ce x # setup to we# going low 10 ns ( t wlel ) (we# setup to ce x # going low) 0 ns w3 t wlwh we# pulse width 40 ns ( t eleh ) (ce x # pulse width) 50 ns w4 t dvwh ( t dveh ) data setup to we# (ce x # ) going high 3 40 ns w5 t avwh ( t aveh ) address setup to we# (ce x # ) going high 3 40 ns w6 t wheh ce x # hold from we# high 10 ns ( t ehwh ) (we# hold from ce x # high) 0 ns w7 t whdx ( t ehdx ) data hold from we# (ce x # ) high 5 ns w8 t whax ( t ehax ) address hold from we# (ce x # ) high 5 ns w9 t whwl we# pulse width high 30 ns ( t ehel ) (ce x # pulse width high) 25 ns w10 t shwh ( t sheh ) wp# v ih setup to we# (ce x # ) going high 100 ns w11 t vpwh ( t vpeh ) v pp setup to we# (ce x # ) going high 2 100 ns w12 t whgl ( t ehgl ) write recovery before read 0 ns w13 t whrl ( t ehrl ) we# high to sts in ry/by# low 90 ns w14 t qvsl wp# v ih hold from valid srd 2,4 0 ns w15 t qvvl v pp hold from valid srd, sts in ry/by# high 2,4 0 ns notes: 1. read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during read-only operations. refer to ac characteristics for read-only operations. 2. sampled, not 100% tested. 3. refer to table 3 for valid a in and d in for block erase, program, or lock-bit configuration. 4. v pp should be at v pph until determination of block erase, program, or lock-bit configuration success (sr.1/3/4/5 = 0). 5. see ordering information for device speeds (valid operational combinations). 6. see figures 13 through 15 for testing characteristics.
28f160s5, 28f320s5 e 46 advance information notes: a. v cc power-up and standby. b. write block erase or program setup. c. write block erase confirm or valid address and data.. d. automated erase or program delay. e. read status register data. f. write read array command. ce x # is the latter of ce 0 # and ce 1 # low or the first of ce 0 # or ce 1 # high. 0608_18 figure 17. ac waveform for write operations
e 28f160s5, 28f320s5 47 advance information 6.2.6 reset operations figure 18. ac waveform for reset operation table 22. reset ac specifications (1) # sym parameter notes min max unit p1 t plph rp# pulse low time (if rp# is tied to v cc , this specification is not applicable) 100 ns p2 t plrh rp# low to reset during block erase, program, or lock- bit configuration 2,3 12 s p3 t 5vph v cc at 4.5v to rp# high 50 s notes: 1. these specifications are valid for all product versions (packages and speeds). 2. if rp# is asserted while a block erase, program, or lock-bit configuration operation is not executing, the reset will complet e within t plph . 3. a reset time, t phqv , is required from the latter of sts in ry/by# mode or rp# going high until outputs are valid.
28f160s5, 28f320s5 e 48 advance information 6.2.7 erase, program, and lock-bit configuration performance table 23. erase/write/lock performance (3,4) 5v 5%, 5v 10% v cc version 5v v pp # sym parameter notes typ (1) max units w16 byte/word program time (using write buffer) 5 2 tbd s w16 t whqv1 t ehqv1 per byte program time (without write buffer) 2 9.24 tbd s w16 t whqv1 t ehqv1 per word program time (without write buffer) 2 9.24 tbd s w16 block program time (byte mode) 2 0.5 tbd sec w16 block program time (word mode) 2 0.38 tbd sec w16 block program time (using write buffer) 2 0.13 tbd sec w16 t whqv2 t ehqv2 block erase time 2 0.34 tbd sec w16 full chip erase time 16 mbit 10.7 sec 32 mbit 21.4 sec w16 t whqv3 t ehqv3 set lock-bit time 2 9.24 tbd s w16 t whqv4 t ehqv4 clear block lock-bits time 2 0.34 tbd sec w16 t whrh1 t ehrh1 program suspend latency time to read 5.6 7 s w16 t whrh2 t ehrh2 erase suspend latency time to read 9.4 13.1 s notes: 1. typical values measured at t a = +25c and nominal voltages. assumes corresponding lock-bits are not set. subject to change based on device characterization. 2. excludes system-level overhead. 3. these performance numbers are valid for all speed versions. 4. sampled but not 100% tested. 5. uses whole buffer.
e 28f160s5, 28f320s5 49 advance information appendix a device nomenclature and ordering information product line designator for all intel flash products package dt = extended temp. 56-lead ssop te = extended temp. 56-lead tsop device type 5 = 5v v cc , 5v v pp e28f1 0 6 s5 - 7 access speed (ns) 0 70 ns (5v, 30 pf), 80 ns (5v) product family s = flashfile? memory device density 160 = 16-mbit 320 = 32-mbit t 0609_20 order code by density valid operational combinations 16 mb 32 mb 10% v cc 100 pf load (16 mb / 32 mb) 5% v cc 30 p f load (16 mb / 32 mb) e28f160s5-70 e28f320s5-90 -80 / -100 -70 / -90 e28f160s5-100 e28f320s5-110 -100 / -110 da28f160s5-70 da28f320s5-90 -80 / -100 -70 / -100 da28f160s5-100 da28f320s5-110 -100 / -110
28f160s5, 28f320s5 e 50 advance information appendix b additional information (1,2) order number document/tool 290608 word-wide flashfile?memory family 28f160s3, 28f320s3 datasheet 292203 ap-645 28f160s3/s5 compatibility with 28f016sa/sv 292204 ap-646 common flash interface and command sets 290528 28f016sv 16-mb (1mbit x 16, 2mbit x 8) flashfile? memory datasheet 290489 28f016sa 16-mb (1mbit x 16, 2mbit x 8) flashfile? memory datasheet 297372 16-mbit flash product family users manual 292123 ap-374 flash memory write protection techniques 292144 ap-393 28f016sv compatibility with 28f016sa 292159 ap-607 multi-site layout planning with intels flashfile? components, including rom capability 292163 ap-610 flash memory in-system code and data update techniques contact intel/distribution sales office cfi - common flash interface reference code notes: 1. please call the intel literature center at (800) 548-4725 to request intel documentation. international customers should contact their local intel or distribution sales office. 2. visit intels world wide web home page at http://www.intel.com for technical documentation and tools.

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